An Integrated 17 GHz Front-End for ISM/WLAN Applications in 0.13 μm CMOS

This paper presents an integrated front-end for ISM/WLAN applications at 17.3 GHz in 0.13 μm standard CMOS. The front-end chip includes an inductive source-degenerated low noise amplifier (LNA), a transformer-based Gilbert-mixer, an intermediate frequency (IF) amplifier and a buffer for the local oscillator (LO) input. The integrated receiver front-end achieves a gain of 34.7 dB, a SSB noise figure of 6.6 dB, an input IP3 of -34.4 dBm and an input 1dB compression point of -39 dBm and consumes only 70 mW at a power supply voltage of 1.5 V. Introduction The trend in the world of the wireless communications is going up to research in faster and high-performance radio frequency (RF) circuits. Sub-micron CMOS is particularly attractive for its low power consumption and high degree of integration. An integrated CMOS chip which combines elementary RF building blocks, such as the RF LNA and a down-conversion mixer, is called the front-end for an RF receiver. The front-end of a wireless receiver must observe the standard for the sensitivity. The input noise of the front-end must be sufficiently low to enable it to detect weak input signals. Also the gain of the receiver must be high enough to fulfill the requirements of wide input dynamic range. The purpose of this work is to develop a high gain CMOS receiver front-end operating at frequencies above 5 GHz such as 17.1-17.3 GHz industrial, scientific and medical (ISM) band. The lower frequency bands (e.g. 2.4 and 5 GHz bands) are being extensively explored for various applications, there are several potentially significant advantages to operation at much higher frequency. One obvious advantage is the larger available bandwidth at high frequencies that is extremely important for wideband wireless communications [1]. LNA